1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a field effect transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same.
2. Description of the Related Art
The recent rapid development of semiconductor technology has been achieved based on the scaling down of field effect-transistors. The scaling down of devices results in the increase of integration degree and improvement of device performance, but also results in undesirable problems due to the scaling down of devices, such as the increase of short channel effects, and the increase of a leakage current, for example, gate leakage current, a drain leakage current, and the like. For these reasons, many efforts have been made on studies to solve the problems involved with the scaling down of devices.
As one method to solve the problems due to the scaling down of devices, there have been proposed a transistor having a gate dielectric layer of partial thickness difference or a notched gate transistor. The notched gate transistor reduces a Miller capacitance interfering with high speed operation of devices, reduces a leakage current from source/drain to a gate, and provides a pocket ion implantation profile successfully so as to improve a short channel effect.
The effects of the notched gate transistor as above result from its structural characteristics, in which a dielectric layer on a channel has a relatively thin thickness, and a dielectric layer on source/drain generating a leakage current has a relatively thick thickness, thereby providing advantages by the scaling down of devices. A method of forming the notched gate transistor requires performing a partial etch process for a gate material. However, the etch process may cause many problems in connection with the scaling down of devices. Therefore, it is required to develop methods of forming a field effect transistor having a gate dielectric layer of partial thickness difference more effectively.
FIGS. 1 through 3 are schematic sectional views illustrating a method of fabricating a conventional transistor having a notched gate.
Referring to FIG. 1, the conventional transistor having a notched gate is formed by processes including forming a relatively thin gate dielectric layer 20 on a semiconductor substrate 10, and forming a relatively thin first gate layer 31 and a relatively thick second gate layer 35 on the gate dielectric layer 20.
Referring to FIG. 2, the second and first gate layers 35, 31, and the gate dielectric layer 20 are patterned such that the first gate layer 31 is recessed from the sidewalls of the second gate layer 35 and the gate dielectric layer 20, thereby forming a notch or groove shape. Referring to FIG. 3, an insulating layer 40 is formed to fill the notch portion, and spacer-etched, thereby forming a spacer shape. The second gate layer 35 is disposed on an insulating layer portion 41 filling the notch.
Specifically, only the gate dielectric-layer 20 having a relatively thin thickness is disposed between the gates 31, 35 and a channel. Between a portion of the gate 35 on a source 51 and a drain 55, and the semiconductor substrate 10, there is disposed a dielectric layer having a relatively thick thickness, that is, the insulating layer portion 41 filling the notch and the gate dielectric layer 20.
The method of fabricating the notched gate transistor includes an operation of partially removing a portion of a gate material, that is, an etch process forming a notch, and the etch process requires precise control for process conditions. However, the precise control for the etch process as above will be presumably difficult to accomplish with the scaling down of devices further developed. Therefore, the approaches used to control the etch process will presumably limit the accomplishment of the scaling down of devices.
Furthermore, a possibility that damage to the lower dielectric layer 20 and the upper second gate layer 35, for example, occurrence of lifting and the like, will be increased in the existing methods of partially removing a gate. Further, difficulties of the occurrence of voids and the like during the process while filling the relevant removed portion, that is, notch portion, will be generated. Therefore, it is required to develop methods of more effectively fabricating the field effect transistor having a gate dielectric layer of partial thickness difference.